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Hermetically Sealed Analog Isolation Amplifier Technical Data
HCPL-7850 HCPL-7851 5962-97557
Features
* Performance Guaranteed over Full Military Temperature Range: -55C to +125C * Manufactured and Tested on a MIL-PRF-38534 Certified Line * Hermetically Sealed Packages * Dual Marked with Device Part Number and DSCC Drawing Number * QML-38534, Class H * HCPL-7840 Function Compatibility * High Common Mode Rejection (CMR): 8 kV/s at VCM = 1000 V * 5% Gain Tolerance * 0.1% Nonlinearity * Low Offset Voltage and Offset Temperature Coefficient * 100 kHz Bandwidth
Applications
* Industrial and Military * High Reliability Systems * Harsh Industrial Environments * Transportation, Medical, and Life Critical Systems * General Purpose Analog Signal Isolation * Motor Phase and Rail Current Sensing * Inverter Current Sensing * Switched Mode Power Supply Signal Isolation * General Purpose Current Sensing and Monitoring
Schematic Diagram
IDD1 VDD1 VIN+ VIN- GND1 1 2 3 4 + - + -
IDD2 8 7 VDD2 VOUT+ VOUT- GND2
6
5
SHIELD
Description
The HCPL-7850/7851 is an isolation amplifier that provides accurate, electrically isolated and amplified representations of voltage and current. When used with a shunt resistor to monitor the motor phase current in a high speed motor drive, the device will offer superior reliability compared with the traditional solutions such as current transformers and Hall-effect sensors. The HCPL-7850/7851
consists of a sigma-delta analogto-digital converter optically coupled to a digital-to-analog converter in a hermetically sealed package. The products are capable of operation and storage over the full military temperature range and can be purchased as either commercial product or with full MIL-PRF-38534 Class H testing or from the appropriate DSCC drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DSCC Qualified Manufacturers List, QML-38534 for Hybrid Microcircuits.
A 0.1 F bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
2
Superior performance in design critical specifications such as common-mode rejection, offset voltage, nonlinearity, and operating temperature make the HCPL-7850/7851 an excellent choice for designing reliable products such as motor controllers and inverters.
Common-mode rejection of 8 kV/s makes the HCPL-7850/ 7851 suitable for noisy electrical environments such as those generated by the high switching rates of power IGBTs.
Low offset voltage together with a low offset voltage temperature coefficient permits accurate use of auto-calibration techniques. Gain tolerance of 5% with 0.1% nonlinearity further provide the performance necessary for accurate feedback and control.
Selection Guide-Package Styles and Lead Configuration Options
Agilent Part Number and Options Commercial MIL-PRF-38534, Class H Standard Lead Finish Solder Dipped Butt Cut/Gold Plate Gull Wing/Soldered SMD Part Number Prescript for all below Either Gold or Solder Gold Plate Solder Dipped Butt Cut/Gold Plate Butt Cut/Soldered Gull Wing/Soldered 59629755701HPX 9755701HPC 9755701HPA 9755701HYC 9755701HYA 9755701HXA HCPL-7850 HCPL-7851 Gold Plate Option #200 Option #100 Option #300
Device Marking
Agilent DESIGNATOR Agilent P/N DSCC SMD* DSCC SMD* PIN ONE/ ESD IDENT
A QYYWWZ XXXXXXXX XXXXXXXXX XXX XXX 50434 * QUALIFIED PARTS ONLY
COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Agilent CAGE CODE*
3
Outline Drawing
9.40 (0.370) 9.91 (0.390) 0.76 (0.030) 1.27 (0.050) 4.32 (0.170) MAX. 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298)
0.51 (0.020) MIN.
3.81 (0.150) MIN.
0.20 (0.008) 0.33 (0.013)
2.29 (0.090) 2.79 (0.110)
0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
7.36 (0.290) 7.87 (0.310)
Hermetic Optocoupler Options
Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310)
200
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead finish. Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads.
300
5.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390)
5.57 (0.180) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX.
5 MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Absolute Maximum Ratings
Storage Temperature (TS) ............................................. -65 to +150C Operating Temperature (TA) .......................................... -55 to +125C Supply Voltages (VDD1, VDD2 ) ......................................... 0.0 to +5.5 V Steady-State Input Voltage (VIN+, VIN-) ...... -2.0 V to VDD1 +0.5 V (1/) 2 Second Transient Input Voltage ...... -6.0 V to V DD1 +0.5 V (1/) Output Voltages (VOUT+, VOUT-) ...........................-0.5 to VDD2 +0.5 V Lead Soldering Temperature (soldering, 10 seconds max.) ...... +260C
ESD Classification
(MIL-STD-883, Method 3015) HCPL-7850/7851 ..... (v); Class 1
Recommended Operating Conditions
Parameter Supply Voltages Input Voltage (See Note 1) Symbol VDD1, VDD2 VIN+, VIN- Min. 4.5 -200 Max. 5.5 +200 Units Volts mV
DC Electrical Specifications
Group A[12] Subgroups 1,2,3 2,3
5
Over recommended operating conditions (TA = -55C to +125C, VIN+ = 0 V, VIN- = 0 V, VDD1 = 5 V and VDD2 = 5 V, unless otherwise specified). Parameter Input Offset Voltage Gain Symbol VOS G Min. -1.0 7.36 Typ.* Max. Units 0.6 8.00 5.0 8.64 mV V/V Test Conditions 4.5 V V DD1, VDD2) 5.5 V Fig. Note 1,2, 3 2
-200 mV VIN+ 200 mV 5,6, 4.5 V (V DD1, VDD2) 7 5.5 V -200 mV VIN+ 200 mV 5,8, 4.5 V (V DD1, VDD2) 9,10, 5.5 V 12 -100 mV VIN+ 100 mV 5,8, 4.5 V (V DD1, VDD2) 9,11, 5.5 V 12 3
1 200 mV Nonlinearity NL200 2,3
7.60
8.00 0.05
8.4 0.8 %
1 100 mV Nonlinearity NL100 2,3
0.05 0.01
0.2 0.2
1 Output Common-Mode Voltage Input Supply Current Output Supply Current Input-Output Insulation Leakage Current Maximum Input Voltage Before Output Clipping Average Input Bias Current Average Input Resistance VOCM 1,2,3 2.20
0.01 2.56
0.1 2.80 V -400 mV VIN+ 400 mV 4.5 V (V DD1, VDD2) 5.5 V 14,17 15,17 RH = 45%, t = 5 sec. VI-O = 1500 Vdc, TA = 25C 4,12 11
IDD1 IDD2 II-O
1,2,3 1,2,3 1
10.7 9.4
15.5 14.5 1.0
mA mA A
|VIN+| MAX
320
mV
IIN RIN
-0.57 480 69
A k dB
13
4
Input DC CMRRIN Common-Mode Rejection Ratio Output Resistance Output Low Voltage Output High Voltage Output ShortCircuit Current Resistance (Input-Output) Capacitance (Input-Output) RO VOL VOH |IOSC| RI-O CI-O
5
1 1.28 3.84 11 1012 2.7
V V mA pF VIN+ = 400 mV VIN+ = -400 mV VOUT = 0 V or VDD2 VI-O = 500 Vdc f = 1 MHz VI-O = 0 Vdc 7 11 4 6
*All typicals are at the nominal operating conditions of VIN+ = 0 V, VIN- = 0 V, TA = 25C, V DD1 = 5 V and VDD2 = 5 V.
6
AC Electrical Specifications
Over recommended operating conditions (TA = -55C to +125C, VIN+ = 0 V, VIN- = 0 V, VDD1 = 5 V and VDD2 = 5 V, unless otherwise specified). Parameter Common Mode Rejection Propagation Delay to 50% Propagation Delay to 90% Rise/Fall Time (10-90%) Small-Signal Bandwidth (-3 dB) Small-Signal Bandwidth (-45) RMS InputReferred Noise Power Supply Rejection Symbol CMR Group A[12] Subgroups 9 Min. 5 Typ.* Max. Units 8 kV/ s 7.5 s Test Conditions VCM = 1 kV 4.5 V (V DD1, VDD2) 5.5 V, TA = 25C Fig. Note 16 8,13
tPD50
9,10,11
3.7
VIN+ = 0 to 100 mV step 18,19 4.5 V (V DD1, VDD2) 5.5 V
tPD90 tR/F f-3 dB
9,10,11 9,10,11 9,10,11 45
5.7 3.4 100
11.0 7.5 kHz 4.5 V (V DD1, VDD2) 5.5 V VIN+ = 200 mVpk-pk sine wave 18,20, 14 21
f-45
31
VN PSR
0.6 570
mVrms In recommended application circuit mVP-P
22,24
9 10
*All typicals are at the nominal operating conditions of VIN+ = 0 V, VIN- = 0 V, TA = 25C, V DD1 = 5 V and VDD2 = 5 V. Notes: 1. If V IN- is brought above VDD1 -2 V with respect to GND1 an internal test mode may be activated. This test mode is not intended for customer use. 2. Exact offset value is dependent on layout of external bypass capacitors. The offset value in the data sheet corresponds to Agilent's recommended layout (see Figures 26 and 27). 3. Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale differential output voltage. 4. Because of the switched capacitor nature of the sigma-delta A/D converter, time averaged values are shown. 5. CMRRIN is defined as the ratio of the gain for differential inputs applied between pins 2 and 3 to the gain for both common mode inputs applied to both pins 2 and 3 with respect to pin 4. 6. When the differential input signal exceeds approximately 320 mV, the outputs will limit at the typical values shown. 7. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or ground. Agilent does not recommend operations under these conditions. 8. CMR (also known as IMR or Isolation Mode Rejection) specifies the minimum rate of rise of a common mode signal applied across the isolation boundary at which small output perturbations begin to occur. These output perturbations can occur with both the rising and falling edges of the common mode waveform and may be of either polarity. A CMR failure is defined as a perturbation exceeding 200 mV at the output of the recommended application circuit (Figure 24). See Applications section for more information on CMR. 9. Output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. Chopper noise results from chopper stabilization of the output op-amps. It occurs at a specific frequency (typically 500 kHz) and is not attenuated by the on-chip output filter. The on-chip filter does eliminate most, but not all, of the sigma-delta quantization noise. An external filter circuit may be easily added to the external post-amplifier to reduce the total RMS output noise. See Applications section for more information. 10. Data sheet value is the amplitude of the transient at the differential output of the HCPL-7850 when a 1 VP-P , 1 MHz square wave with 100 ns rise and fall times (measured at pins 1 and 8) is applied to both VDD1 and VDD2. 11. Device considered a two-terminal device: Pins 1, 2, 3, and 4 are shorted together and pins 5, 6, 7, and 8 are shorted together. 12. Commercial parts receive 100% testing at 25C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25C, +125C and -55C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 13. Parameters are tested as part of device initial characterization and after design and process changes only. Parameters are guaranteed to limits specified for all lots not specifically tested. 14. The f-3dB test is guaranteed by the TRISE test.
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VDD1
VDD2
+15 V 0.1 F
1
8
0.1 F
2 HCPL-7850 3 6 7 10 K +
0.1 F
10 K
VOUT
- AD624CD GAIN = 100
4
5
0.47 F
0.47 F -15 V
0.1 F
Figure 1. Input Offset Voltage Test Circuit.
VOS - INPUT OFFSET CHANGE - mV
1.5
vs. VDD2 (VDD1 = 5 V) 0.6 TA = 25C 0.3
VO - OUTPUT VOLTAGE - V
VDD1 = 5 V VDD2 = 5 V
VOS - INPUT OFFSET CHANGE - mV
2.0
0.9 vs. VDD1 (VDD2 = 5 V)
4.0 3.5
NEGATIVE OUTPUT POSITIVE OUTPUT
3.0 2.5 2.0 1.5 1.0 -0.6 VDD1 = 5 V VDD2 = 5 V TA = 25C -0.4 -0.2 0 0.2 0.4 0.6 VIN - INPUT VOLTAGE - V
1.0
0.5
0
0
-0.5 -60
-20
20
60
100
140
-0.3 4.4
4.6
4.8
5.0
5.2
5.4
5.6
TA - TEMPERATURE - C
VDD - SUPPLY VOLTAGE - V
Figure 2. Input Offset Change vs. Temperature.
Figure 3. Input Offset Change vs. V DD1 and VDD2.
Figure 4. Output Voltages vs. Input Voltage.
8
VDD1
VDD2
+15 V 0.1 F
+15 V 0.1 F
1
8
0.1 F VIN 404
2 HCPL-7850 3 6 7
0.1 F
10 K + +
13.2 0.01 F
10 K
VOUT
- AD624CD GAIN = 4 - AD624CD GAIN = 10
4
5
0.47 F
0.47 F -15 V
0.1 F
0.1 F
-15 V
10 K
0.47 F
Figure 5. Gain and Nonlinearity Test Circuit.
0.05 VDD1 = 5 V VDD2 = 5 V
G - GAIN CHANGE - %
0.10 0.08
G - GAIN CHANGE - %
NL ERROR - % OF FULL SCALE
0.15
vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) TA = 25C
200 mV ERROR 100 mV ERROR 0.10 VDD1 = 5 V VDD2 = 5 V VIN- = 0 V TA = 25C
0
0.06 0.04 0.02 0 -0.02 -0.04
-0.05
0.05
-0.10
0
-0.15 -0.20 -60
-0.05
-20
20
60
100
140
-0.06 4.4
4.6
4.8
5.0
5.2
5.4
5.6
-0.10 -0.2
-0.1
0
0.1
0.2
TA - TEMPERATURE - C
VDD - SUPPLY VOLTAGE - V
VIN+ - INPUT VOLTAGE - V
Figure 6. Gain Change vs. Temperature.
Figure 7. Gain Change vs. V DD1 and V DD2.
Figure 8. Nonlinearity Error Plot vs. Input Voltage.
9
0.4 VDD1 = 5 V VDD2 = 5 V VIN- = 0 V TA = 25 C 200 mV 100 mV
0.07 vs. VDD1 (VDD2 = 5 V) NL - NONLINEARITY - % NL - NONLINEARITY - % vs. VDD2 (VDD1 = 5 V) 0.06 TA = 25C 0.05
0.025 vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) 0.020 TA = 25C 0.015
NL - NONLINEARITY - %
0.3
0.2
0.1
0.04
0.010
0 -60
-20
20
60
100
140
0 4.4
4.6
4.8
5.0
5.2
5.4
5.6
0.005 4.4
4.6
4.8
5.0
5.2
5.4
5.6
TA - TEMPERATURE - C
VDD - SUPPLY VOLTAGE - V
VDD - SUPPLY VOLTAGE - V
Figure 9. Nonlinearity vs. Temperature.
Figure 10. 200 mV Nonlinearity vs. V DD1 and VDD2.
Figure 11. 100 mV Nonlinearity vs. VDD1 and VDD2.
IDD1 - INPUT SUPPLY CURRENT - mA
2
11 TA = 25C 10
5.00
IIN - INPUT CURRENT - mA
NL - NONLINEARITY - %
TA = 25C
0 -2 -4 -6 -8 -10 -6 VDD1 = 5 V VDD2 = 5 V VIN- = 0 V TA = 25C
0.50
9
8 VDD1 = 5 V VDD2 = 5 V VIN- = 0 V -0.2 0 0.2 0.4
0.05 VDD1 = 5 V VDD2 = 5 V 0.01 0 0.10 0.20 0.30 0.40
7
-4
-2
0
2
4
6
6 -0.4
FS - FULL-SCALE INPUT VOLTAGE - V
VIN+ - INPUT VOLTAGE - V
VIN+ - INPUT VOLTAGE - V
Figure 12. Nonlinearity vs. Full-Scale Input Voltage.
Figure 13. Input Current vs. Input Voltage.
Figure 14. Input Supply Current vs. Input Voltage.
10
10 K
78L05 IN OUT
IDD2 - OUTPUT SUPPLY CURRENT - mA
VDD2
150 pF +15 V
10.0 VDD1 = 5 V VDD2 = 5 V VIN- = 0 V
0.1 F
0.1 F
1
8
0.1 F 0.1 F
2 9V 3 HCPL-7850
7
2K -
9.5
6
2K
VOUT
+ MC34081
9.0 TA = 25C 8.5
4 5 10 K
0.1 F
PULSE GEN.
8.0 -0.4 -0.2 0 0.2 0.4
+ -
150 pF
-15 V
VIN+ - INPUT VOLTAGE - V
VCM
Figure 15. Output Supply Current vs. Input Voltage.
Figure 16. Common Mode Rejection Test Circuit.
10 K
VDD1
IDD - POWER SUPPLY CURRENT - mA
VDD2
+15 V 0.1 F
20 IDD1 IDD2 15 VDD1 = 5 V VDD2 = 5 V VIN+ = 320 mV VIN- = 0 V
0.1 F
1 8
0.1 F
2 HCPL-7850 7 2K - 3 6 2K
VIN
VOUT
+ MC34081
10
0.01 F
5
4
5 10 K
0.1 F
0 -60
-20
20
60
100
140
VIN IMPEDANCE LESS THAN 10 .
-15 V
TA - TEMPERATURE - C
Figure 17. Input and Output Supply Current vs. Temperature.
Figure 18. Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit.
11
10 RELATIVE AMPLITUDE - dB 9 8 t - TIME - s 7 6 5 4 3 VIN- = 0 V VIN+ = 0 TO 100 mV STEP 2 -60 -40 -20 0 20 40 60 80 100 120 140 TA - TEMPERATURE - C DELAY TO 90% DELAY TO 50% RISE/FALL TIME VDD1 = 5 V VDD2 = 5 V
0
-1 VDD1 = 5 V VDD2 = 5 V TA = 25 C -2
-3
-4
1
5
10
50 100
500
f - FREQUENCY - kHz
Figure 19. Propagation Delays and Rise/Fall Time vs. Temperature.
Figure 20. Amplitude Response vs. Frequency.
160
f (-3 dB) - 3 dB BANDWIDTH - kHz
VN - RMS INPUT-REFERRED NOISE - mV
2.5 VIN+ = 200 mV VIN+ = 100 mV VIN+ = 0 mV TA = 25C VDD1 = 5 V VDD2 = 5 V
140 120 100 80 60 40 -60 -40 -20 0
VDD1 = 5 V VDD2 = 5 V
2.0
1.5
1.0
0.5 0
20 40 60 80 100 120 140
5
10
50
100
500
TA - TEMPERATURE - C
f - FREQUENCY - KHz
Figure 21. 3 dB Bandwidth vs. Temperature.
Figure 22. RMS Input-Referred Noise vs. Recommended Application Circuit Bandwidth.
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VOLTAGE REGULATOR
CLOCK GENERATOR ISOLATION BOUNDARY
VOLTAGE REGULATOR
ISO-AMP INPUT
MODULATOR
ENCODER
LED DRIVE CIRCUIT
DETECTOR CIRCUIT
DECODER AND D/A
FILTER
ISO-AMP OUTPUT
Figure 23. HCPL-7850 Block Diagram.
POSITIVE FLOATING SUPPLY HV+ GATE DRIVE CIRCUIT U1 78L05 IN C1 0.1 F OUT C2 0.1 F
2 7 U2 6 1 8 C4
C5 150 pF
***
R3 10.0 K
+5 V +15 V C8 0.1 F
0.1 F
R1 2.00 K R2 2.00 K - U3 + MC34081
R5 68
C3 0.01 3 F
VOUT
MOTOR ***
+
-
4 HCPL-7850
5 C6 150 pF R4 10.0 K
C7 0.1 F
RSENSE
-15 V
*** HV-
Figure 24. Recommended Application Circuit.
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Applications Information
Functional Description Figure 23 shows the primary functional blocks of the HCPL7850. In operation, the sigmadelta modulator converts the analog input signal into a highspeed serial bit stream. The time average of this bit stream is directly proportional to the input signal. This stream of digital data is encoded and optically transmitted to the detector circuit. The detected signal is decoded and converted back into an analog signal, which is filtered to obtain the final output signal.
Application Circuit The recommended application circuit is shown in Figure 24. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple three-terminal voltage regulator (U1). The voltage from the current sensing resistor, or shunt (Rsense), is applied to the input of the HCPL-7850 through an RC anti-aliasing filter (R5, C3). And finally, the differential output of the isolation amplifier is converted to a ground-referenced
C5 150 pF
single-ended output voltage with a simple differential amplifier circuit (U3 and associated components). Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. Supplies and Bypassing As mentioned above, an inexpensive three-terminal regulator can be used to reduce the gate-drive power supply voltage to 5 V. To help attenuate high frequency power supply noise or ripple, a resistor or
+5 V
R3 10.0 K
+5 V +5 V
R4A 20.0 K 1 8 C4
R5
C2
C4
C8 0.1 F
C3
0.1 F
2 U2 3 6 7 R1 10.0 K R2 10.0 K 4 HCPL-7850 5 C6 150 pF R4B 20.0 K
TO VDD1 TO RSENSE+ TO RSENSE- TO VDD2 VOUT+ VOUT-
- U3 + MC34071
VOUT
Figure 26. Top Layer of Printed Circuit Board Layout.
Figure 25. Single-Supply Post-Amplifier Circuit. Figure 27. Bottom Layer of a Printed Circuit Board Layout.
27 1k 1k VDD VIN+ VIN- GND 3 4 - 1 2 + + - 8 VDD 7 VOUT+
27 1k 0.1 F 1k (+) (-) VDD 5.5 VDC
6
VOUT- 5 GND
CONDITIONS: I CC=17.5mA T A=+125C
Figure 28. Operating Circuit for Burn-In and Steady State Life Tests.
14
inductor can be used in series with the input of the regulator to form a low-pass filter with the regulator's input bypass capacitor. As shown in Figure 24, a 0.1 F bypass capacitor (C2, C4) should be located as close as possible to the input and output power supply pins of the HCPL-7850. The bypass capacitors are required because of the highspeed digital nature of the signals inside the isolation amplifier. A 0.01 F bypass capacitor (C3) is also recommended at the input pin(s) due to the switchedcapacitor nature of the input circuit. The input bypass capacitor should be at least 1000 pF to maintain gain accuracy of the isolation amplifier. Inductive coupling between the input power-supply capacitor and the input circuit, including the input bypass capacitor and the input leads of the HCPL-7850, can introduce additional DC offset in the circuit. Several steps can be taken to minimize the mutual coupling between the two parts of the circuit, thereby improving the offset performance of the design. Separate the two bypass capacitors C2 and C3 as much as possible (even putting them on opposite sides of the PC board), while keeping the total lead lengths, including traces, of each bypass capacitor less than 20 mm. PC board traces should be made as short as possible and placed close together or over ground plane to minimize loop area and pickup of stray magnetic fields. Avoid using sockets, as they will typically increase both loop area and inductance. And finally, using capacitors with small body size and orienting
them perpendicular to each other on the PC board can also help. For more information concerning this effect, see Application Note 1078, Designing with Agilent Technologies Isolation Amplifiers. Shunt Resistor Selections The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). The value of the shunt should be chosen as a compromise between minimizing power dissipation by making the shunt resistance smaller and improving circuit accuracy by making it larger and utilizing the full input range of the HCPL7850. Agilent Technologies recommends four different shunts which can be used to sense average currents in motor drives up to 35 A and 35 hp. Table 1 shows the maximum current and horsepower range for each of the LVR-series shunts from Dale. Even higher currents can be sensed with lower value shunts available from vendors such as Dale, IRC, and Isotek (Isabellenhuette). When sensing currents large enough to cause significant heating of the shunt, the temperature coefficient of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. Using a heat sink for the shunt or using a shunt with a lower tempco can help minimize this effect. The Application Note 1078, Designing with Agilent Technologies Isolation Amplifiers, contains additional information on designing with current shunts.
The recommended method for connecting the isolation amplifier to the shunt resistor is shown in Figure 24. Pin 2 (VIN+) is connected to the positive terminal of the shunt resistor, while pin 3 (VIN-) is shorted to pin 4 (GND1), with the powersupply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of wires or PC board traces to connect the isolation amplifier circuit to the shunt resistor. In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting pin 3 to the negative terminal of the shunt resistor separate from the power supply return path. When connected this way, both input pins should be bypassed. Whether two or three wires are used, it is recommended that twisted-pair wire or very close PC board traces be used to connect the current shunt to the isolation amplifier circuit to minimize electromagnetic interference to the sense signal. The 68 resistor in series with the input lead forms a low-pass anti-aliasing filter with the input bypass capacitor with a 200 kHz bandwidth. The resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the wires or traces connecting the two. Undampened ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device. To be
15
effective, the damping resistor should be at least 39 . PC Board Layout In addition to affecting offset, the layout of the PC board can also affect the common mode rejection (CMR) performance of the isolation amplifier, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the printed circuit board (PCB) should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground plane on the PCB does not pass directly below the HCPL-7850. Using surface mount components can help achieve many of the PCB objectives discussed in the preceding paragraphs. An example throughhole PCB layout illustrating some of the more important layout recommendations is shown in Figures 26 and 27. See Applications Note 1078, Designing with Agilent Technologies Isolation Amplifiers, for more information on PCB layout consideration. Post-Amplifier Circuit The recommended application circuit (Figure 24) includes a post-amplifier circuit that serves three functions: to reference the output signal to the desired level (usually ground), to amplify the signal to appropriate levels, and to help filter output noise. The particular op-amp used in the post-amp is not critical; however, it should have low enough offset and high enough bandwidth and slew rate so that it does not adversely affect circuit performance. The offset of the op-amp should be low relative to
the output offset of the HCPL7850, or less than about 5 mV. To maintain overall circuit bandwidth, the post-amplifier circuit should have a bandwidth at least twice the minimum bandwidth of the isolation amplifier, or about 200 kHz. To obtain a bandwidth of 200 kHz with a gain of 5, the op-amp should have a gain-bandwidth greater than 1 mHz. The postamplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter. These capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier (doubling the capacitor values halves the circuit bandwidth). The component values shown in Figure 24 form a differential amplifier with a gain of 5 and a cutoff frequency of approximately 100 kHz, and were chosen as a compromise between low noise and fast response times. The overall recommended application circuit has a bandwidth of 66 kHz, a rise time of 5.2 s and a delay to 90% of 8.5 s. The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and gain tolerance for the overall circuit. Resistor networks with even better ratio tolerances can be used which offer better performance, as well as reducing the total component count and board space. The post-amplifier circuit can be easily modified to allow for single-supply operation. Figure 25 shows a schematic for a post amplifier for use in 5 V single
supply applications. One additional resistor is needed and the gain is decreased to 1 to allow circuit operation over the full input voltage range. See Application Note 1078, Designing with Agilent Technologies Isolation Amplifiers, for more information on the post-amplifier circuit. Other Information As mentioned above, reducing the bandwidth of the post amplifier circuit reduces the amount of output noise. Figure 22 shows how the output noise changes as a function of the post-amplifier bandwidth. The post-amplifier circuit exhibits a first-order lowpass filter characteristic. For the same filter bandwidth, a higherorder filter can achieve even better attenuation of modulation noise due to the second-order noise shaping of the sigma-delta modulator. For more information on the noise characteristics of the HCPL-7850, see Application Note 1078, Designing with Agilent Technologies Isolation Amplifiers. The HCPL-7850 can also be used to isolate signals with amplitudes larger than its recommended input range through the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 K so that the input resistance (480 K) and input bias current (0.6 A) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 68 series damping resistor is not. (The resistance of the voltage divider provides the same function.) The low pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth.
Table 1. Current Shunt Summary. Shunt Resistance 50 m 20 m 10 m 5 m Maximum Power Dissipation 3W 3W 3W 5W Maximum Average Current 3A 8A 15 A 35 A Maximum Horsepower Range 0.8 to 3.0 hp 2.2 to 8.0 hp 4.1 to 15 hp 9.6 to 35 hp
Shunt Resistor Part Number LVR-3.05-1% LVR-3.02-1% LVR-3.01-1% LVR-5.005-1%
MIL-PRF-38534 Class H and DSCC SMD Test Program Agilent Technologies' Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Class H. Class H devices are also in compliance with DSCC drawing 5962-97557. Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2000 Agilent Technologies Osoletes 5966-2716E 5968-9405E (11/00)

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